2006 · 133 citations · 15 references
EngineeringComputer EngineeringElectrical EngineeringAgingMemoryMicroelectronicsDevice ReliabilityMemory DevicesMemory ModelingReliability ModelingSemiconductor ReliabilityActivation EnergyActivation Energy DeterminationDelay EffectsErase CyclingFlash MemoryFlash Memory ReliabilityMemory ReliabilityProgram Cycling
Dielectric damage caused by program/erase cycling partially recovers during the delays between cycles. This paper characterizes the effect of these delays on the charge-detrapping data-retention mechanism. Delay effects are temperature accelerated with an activation energy of 1.1 eV. Using this activation energy, qualification cycling temperature and time can be chosen to emulate the rate of cycling expected in field use. Retention lifetime can be more than an order of magnitude greater after cycling with realistic delays than with the minimal delays common in qualification stresses. For purposes of extrapolating from one cycling rate or temperature to another, an empirical accelerated reliability model is proposed, based on a "unified detrapping metric" or UDM. The UDM comprehends the effects of cycle count, cycle rate, cycling temperature, retention time, and retention temperature
15
A new reliability model for post-cycling charge retention of flash memories
Hanmant Belgal, Nick Righos, I. Kalastirsky et al. · 2003 · 108 citations
Engineering, Computer Engineering, Electrical Engineering +15
Novel read disturb failure mechanism induced by FLASH cycling
Adam Brand, Kehuey Wu, Shijie Pan et al. · 1993 · 88 citations