2006 · 38 citations · 7 references
EngineeringElectrical EngineeringManufacturing EngineeringMicroelectronicsMicrofabricationSensorsChip PackagingCmos Circuit DesignIntegrated Circuit DesignIntegrated Circuit DevicesIntegrated Circuit FabricationInterconnect TechnologyCmos Fabrication ProcessesCmos Image SensorsFabrication TechniquesInterconnect FabricationLaser AblationLow Cost IntegrationPattern PlatingSilicon
If vertical interconnections could be fabricated at low cost, it would bring about many advantages, such as miniaturization and lower a height of the package. Our through-chip via (TCV) technology to fabricate vertical interconnections consists of a first via drilling by laser ablation (silicon drilling), followed by dielectric film lamination, a second via drilling by laser ablation (dielectric film drilling) and pattern plating of Cu. Our technology, being based on the printed-circuit-board fabrication process, has no need for expensive wafer fabrication techniques such as RIE, CVD and CMP. Thus, it enables the realization of the fabrication of through-chip vertical interconnections at low cost. In this paper, we describe the details of our process and its application in the fabrication of CMOS image sensor.
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Laser-cleaning techniques for removal of surface particulates
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Thermal Response of Metals to Ultrashort-Pulse Laser Excitation
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Three dimensional metallization for vertically integrated circuits
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Process integration of 3D chip stack with vertical interconnection
Kenji Takahashi, Yuichi Taguchi, M. Tomisaka et al. · 2004 · 84 citations
Engineering, Electrical Engineering, Materials Engineering +17