Novel Low Cost Integration of Through Chip Interconnection and Application to CMOS Image Sensor

Masahiro Sekiguchi, Hideo Numata, Naoki Sato, T. Shirakawa, M. Matsuo, Hiroshi Yoshikawa, Masahiro Yanagida, H. Nakayoshi, Kenji Takahashi

2006 · 38 citations · 7 references

Concepts

Abstract

If vertical interconnections could be fabricated at low cost, it would bring about many advantages, such as miniaturization and lower a height of the package. Our through-chip via (TCV) technology to fabricate vertical interconnections consists of a first via drilling by laser ablation (silicon drilling), followed by dielectric film lamination, a second via drilling by laser ablation (dielectric film drilling) and pattern plating of Cu. Our technology, being based on the printed-circuit-board fabrication process, has no need for expensive wafer fabrication techniques such as RIE, CVD and CMP. Thus, it enables the realization of the fabrication of through-chip vertical interconnections at low cost. In this paper, we describe the details of our process and its application in the fabrication of CMOS image sensor.

References

7