Suppression of boron penetration in p/sup +/ polysilicon gate P-MOSFETs using low-temperature gate-oxide N/sub 2/O anneal

Abstract

It has been reported that high-temperature (/spl sim/1100/spl deg/C) N/sub 2/O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900/spl sim/950/spl deg/C) N/sub 2/O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO/sub 2/ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60/spl sim/110 /spl Aring/ gate oxides, a certain amount of nitrogen (/spl sim/2.2%) incorporated near the Si/SiO/sub 2/ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>