IEEE Transactions on Nuclear Science · 2008 · 59 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringFault-tolerant ComputingMicroelectronicsSemiconductor DevicesBuilt-in Self-testCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDevice ReliabilityHardware Fault ToleranceIntegrated Circuit DesignBlock Ram ArchitectureCmos ReliabilityError MitigationFault-tolerant ArchitectureLeakage Error MitigationRadiation-induced Error MitigationSoft Error Mitigation
Recent measurements of the SEU (single-event upset) cross-section for 6 T SRAMs fabricated in a nano-scale commercial CMOS process were performed. Results indicated that the dominant upset mechanism was associated with multiple-cell upsets (MCUs) strikes on PMOS transistors. The dominance of the MCU cross section favors the use of a block architecture with widely spaced word bits and the use of EDAC (error detect and correct) along with periodic memory scrubbing to prevent the integration of single-bit errors.
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