Numerical modeling of through silicon via (TSV) stacked module with micro bump interconnect for biomedical device

Abstract

A two-die stacked silicon module with TSV has been developed in this work. Thermal-mechanical analysis has been performed and TSV interconnect design is optimized. Multiple chips representing different functional circuits are assembled using flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the burrier copper via is exposed by special backgrinding process. A two-dimensional plane strain analysis using the global-local technique, based on St. Venant's principle, is performed on the diagonal cross-section of the wafer. The thermal-mechanical modeling has shown that the shear stress S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">xy</sub> at the micro-bump, compressive stress S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> at the interconnection and shear stress S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">xy</sub> at the TSV are reduced for off-pad via as compared to on-pad via. This is because the CTE mismatch between the micro-bump and TSV is no longer effective when the TSV is offset. Also the work presented that the offset distance of the off-pad via does not have an impact to the compressive stress S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> and shear stress S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">xy</sub> at the interconnection. There are also no significant changes in the shear stress S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">xy</sub> at the TSV as the off-pad via moves outward to the die edge. As we knows that the bending stress S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> is a major factor contributing to die cracking due to coefficient of thermal expansion (CTE) mismatch. Our simulation results showed that the bending stress S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> of the top die and bottom die was not affected by increasing the offset distance of the off-pad via even to the die edge. Thus it is an advantage to plate the through-silicon-via away from the micro-bump to avoid stresses complication arises from CTE mismatch.