V. Kripesh - Concepedia

Author

V. Kripesh

Institute of Microelectronics

Also Known As

V Kripesh, V. KRIPESH, V. Kripesh, V. P. Kripesh, VAIDYANATHAN KRIPESH, Vaidyanathan Kripesh

124

Publications

2.2K

Citations

H-Index

Concepts

All Affiliations

Institute of Microelectronics Agency for Science, Technology and Research Singapore Science Park National University of Singapore Nanyang Technological University

About

V. Kripesh is an author at Institute of Microelectronics specializing in engineering, electronic packaging, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	26	56	2K
2	Electrical Engineering	23	45	1.6K
3	Applied Physics	16	27	771
4	Computer Engineering	14	18	848
5	Biomedical Engineering	2	2	29

V. Kripesh

Publications

Citations

H-Index

Page 1

	Year	Citations
Single-wall carbon nanotube (SWCNT) functionalized Sn–Ag–Cu lead-free composite solders Mohan Kumar Kesarla, V. Kripesh, A.A.O. Tay Journal of Alloys and Compounds Materials ScienceEngineeringCarbon-based MaterialNanomaterialsCarbon Materials	2006	166
High RF performance TSV silicon carrier for high frequency application Soon Wee Ho, Seung Wook Yoon, Qiaoer Zhou, EngineeringRadio FrequencyHigh Frequency SignalHigh FrequencyInterconnect (Integrated Circuits)	2008	131
Development of 3-D Silicon Module With TSV for System in Packaging Navas Khan, V. S. Rao, Sharon Pei-Siang Lim, IEEE Transactions on Components and Packaging Technologies EngineeringRadio FrequencyIntegrated CircuitsInterconnect (Integrated Circuits)Advanced Packaging (Semiconductors)	2010	119
Development of through silicon via (TSV) interposer technology for large die (21&#x00D7;21mm) fine-pitch Cu/low-k FCBGA package Xiaowu Zhang, T.C. Chai, John H. Lau, EngineeringComputer ArchitectureLarge DieInterconnect (Integrated Circuits)Advanced Packaging (Semiconductors)	2009	109
Electromigration in flip chip solder joints having a thick Cu column bump and a shallow solder interconnect Jae-Woong Nah, Jong-ook Suh, K. N. Tu, Journal of Applied Physics Advanced PackagingMaterials ScienceElectrical EngineeringElectromigration TechniqueEngineering	2006	99
Development of 3D silicon module with TSV for system in packaging Navas Khan, Vempati Srinivasa Rao, Samule Lim, Advanced Packaging3D Ic ArchitectureElectrical EngineeringChip-scale PackageEngineering	2008	78
Three-dimensional system-in-package using stacked silicon platform technology V. Kripesh, Seung Wook Yoon, V.P. Ganesh, IEEE Transactions on Advanced Packaging EngineeringComputer ArchitectureGood DiceDaisy ChainAdvanced Packaging (Semiconductors)	2005	76
Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects Aibin Yu, John H. Lau, Soon Wee Ho, IEEE Transactions on Components Packaging and Manufacturing Technology EngineeringIntegrated CircuitsInterconnect (Integrated Circuits)Wafer Scale ProcessingAdvanced Packaging (Semiconductors)	2011	65
3-D Packaging With Through-Silicon Via (TSV) for Electrical and Fluidic Interconnections Navas Khan, Li Yu, Tan Siow Pin, IEEE Transactions on Components Packaging and Manufacturing Technology EngineeringChip CarrierLiquid Metal Cooling3-D PackageFluidic Interconnections	2013	59
Study of 15&#x00B5;m pitch solder microbumps for 3D IC integration Aibin Yu, John H. Lau, Soon Wee Ho, EngineeringUltra Fine PitchIntegrated CircuitsWafer Scale ProcessingAdvanced Packaging (Semiconductors)	2009	57

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