A-RAM Memory Cell: Concept and Operation

Abstract

Capacitorless single-transistor (1T) DRAM cells are envisioned for replacing the conventional DRAMs where the storage capacitor can hardly be further miniaturized. We propose a totally different 1T-DRAM cell, named A-RAM, which is compatible with SOI CMOS deep scaling. Its novelty comes from the partitioning of the transistor body into two distinct ultrathin regions separated by a thin dielectric. The holes are physically confined in the upper semibody and govern the electron current flowing into the lower semibody. The systematic simulations show that the A-RAM is attractive for low-power and embedded memory applications since it exhibits enhanced state definition, retention, scalability, and simple waveforms for word and bit lines.