Maximizing reliable performance of advanced CMOS circuits—A case study

Abstract

We consider in detail the aspects of maximizing application performance while maintaining its sufficient reliability on the specific case of serially connected nFETs. Serially connected nFETs used in some digital CMOS applications, such as SRAM decoder circuits, and dynamic logic, are vulnerable to Positive Bias Temperature Instability (PBTI). Here we discuss the impact of PBTI frequency and workload on high-k/metal gate nFETs in terms of Capture and Emission Time (CET) maps and quantitatively explain the degradation of our test circuit. This constitutes one of the first validations of the CET map-based methodology on a real silicon circuit. From individual trapping events in deeply scaled nFETs we then project PBTI distributions at 10 years. We further show that at increased supply voltage the serially connected nFET speed degradation is outweighed by signal transfer speedup, resulting in a net performance improvement. Finally, we discuss other degradation mechanisms and conclude the reliability in the studied case will be limited by hard gate oxide breakdown.