Impact of dual-k spacer on analog performance of underlap FinFET

Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance

F. Balestra, S. Cristoloveanu, M. Benachir et al. · IEEE Electron Device Letters · 1987 · 747 citations

Device Modeling, Electrical Engineering, Engineering +13

A g/sub m//I/sub D/ based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA

Fernando Silveira, Denis Flandre, P.G.A. Jespers · IEEE Journal of Solid-State Circuits · 1996 · 646 citations

Electrical Engineering, Engineering, Vlsi Design +13

Analysis of the Parasitic S/D Resistance in Multiple-Gate FETs

Abhisek Dixit, Anil Kottantharayil, Nadine Collaert et al. · IEEE Transactions on Electron Devices · 2005 · 354 citations

Device Modeling, Electrical Engineering, Selective Epitaxial Growth +10

Nanoscale FinFETs with gate-source/drain underlap

Vishal Trivedi, J.G. Fossum, M.M. Chowdhury · IEEE Transactions on Electron Devices · 2004 · 270 citations

Device Modeling, Electrical Engineering, Effective Underlap +10

Extension and source/drain design for high-performance finFET devices

J. Kedzierski, M. Ieong, E. Nowak et al. · IEEE Transactions on Electron Devices · 2003 · 244 citations

Low-power Electronics, Extension Implants, Electrical Engineering +14