High aspect ratio and low capacitance through-silicon-vias (TSVs) with polymer insulation layers

Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs

Guruprasad Katti, Michele Stucchi, K. De Meyer et al. · IEEE Transactions on Electron Devices · 2009 · 579 citations

Three-dimensional Ics, Engineering, Silicon Vias +19

Uniaxial-process-induced strained-Si: extending the CMOS roadmap

Scott E. Thompson, Guangyu Sun, Youn Sung Choi et al. · IEEE Transactions on Electron Devices · 2006 · 578 citations

Electrical Engineering, Engineering, Nanoelectronics +12

Three-dimensional silicon integration

John Knickerbocker, Paul Andry, B. Dang et al. · IBM Journal of Research and Development · 2008 · 487 citations

Engineering, Device Integration, Integrated Circuits +22

3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems

Jian‐Qiang Lu · Proceedings of the IEEE · 2009 · 311 citations

Engineering, Device Integration, Biomedical Engineering +20

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

Geert Van der Plas, Paresh Limaye, Igor Loi et al. · IEEE Journal of Solid-State Circuits · 2010 · 308 citations

Engineering, Vlsi Design, 3-D Chip Stacks +17