Uniaxial-process-induced strained-Si: extending the CMOS roadmap

TLDR

This paper reviews the history of strained‑silicon and the widespread adoption of uniaxial‑process‑induced strain in high‑performance 90‑, 65‑, and 45‑nm logic technologies. Strained‑Si hole mobility data are analyzed using six‑band k·p calculations for uniaxial longitudinal compressive and biaxial stresses on [001] and [110] wafers. The findings show that low in‑plane and high out‑of‑plane effective masses, a dense top band, and longitudinal compressive stress on [001] or [110] wafers with <110> channels can boost hole mobility up to ~4× for uniaxial stress on (100) wafers and ~2× for biaxial stress on (100) wafers.

Abstract

This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are analyzed using six band k/spl middot/p calculations for stresses of technological importance: uniaxial longitudinal compressive and biaxial stress on [001] and [110] wafers. The calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all important for large hole mobility enhancement. This work suggests longitudinal compressive stress on [001] or [110] wafers and <110> channel direction offers the most favorable band structure for holes. The maximum Si inversion-layer hole mobility enhancement is estimated to be /spl sim/ 4 times higher for uniaxial stress on (100) wafer and /spl sim/ 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a [110] wafer.