Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 2002 · 11 citations · 18 references
EngineeringMaterials EngineeringMaterials ScienceElectronic MaterialsSemiconductor DevicesSemiconductor MaterialsDefects In Electronic MaterialsDevice CharacterizationDevice ScalingIon ImplantationSemiconductor DefectsSemiconductor InterfacesExtended DefectsInterstitialsIon Implantation EffectsSemiconductor TechnologySilicon DefectsSilicon InterfacesSilicon WafersSilicon-on-insulator Technology
As device dimensions continue to be scaled, incorporation of silicon-on-insulator (SOI) as mainstream complementary metal–oxide–semiconductor technology also increases. This experiment set out to further investigate the effect of the surface Si/buried oxide (BOX) interface on the formation and dissolution of extended defects in SOI. UNIBOND® wafers were thinned to 300, 700, and 1600 Å. Si+ ion implantation was performed from 5 to 40 keV with a constant, nonamorphizing dose of 2×1014 cm−2. Inert ambient furnace anneals were performed at 750 °C for times of 5 min up to 8 h. Transmission electron microscopy was used to study the evolution of extended defects, as well as to quantify the number of trapped interstitials. It is observed that the surface Si/BOX interface does not enhance the dissolution rate of extended defects unless ⩾15% of the dose is truncated by the BOX. Further, no reduction in the trapped interstitial concentration is seen unless ⩾6% of the dose is truncated. It is concluded that the surface Si/BOX interface does not serve as a significant sink for interstitial recombination, as long as the interstitial profile is mostly confined to the surface Si layer.
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