2011 · 58 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsChannel EngineeringCmos ScalingDevice OptimizationLow-power Cmos DesignLow-temperature ProcessingUltra-low-power Cmos
We have achieved aggressive reduction of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> variation and V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD-min</inf> by a sophisticated planar bulk MOSFET named ‘Deeply Depleted Channel ™ (DDC)’. The DDC transistor has been successfully integrated into an existing 65nm CMOS platform by combining layered channel formation and low temperature processing. The 2x reduction of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> variation in 65nm-node has been demonstrated by matching SRAM pair transistors, 2x improvement in SRAM static noise margin (SNM) and 300 mV V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD-min</inf> reduction of 576Kb SRAM macros to 0.425 V using conventional 6T cell layout.
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