L. Shifren

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry, R. Chau, Changhwan Choi et al. · 2007 · 829 citations

Engineering, Computer Engineering, Electrical Engineering +17

ASAP7: A 7-nm finFET predictive process design kit

Lawrence T. Clark, Vinay Vashishtha, L. Shifren et al. · Microelectronics Journal · 2016 · 736 citations · Full text

Engineering, Electrical Engineering, Microfabrication +13

A 90-nm logic technology featuring strained-silicon

Scott E. Thompson, M Armstrong, C. Auth et al. · IEEE Transactions on Electron Devices · 2004 · 666 citations

Engineering, Electrical Engineering, Materials Science +17

A Logic Nanotechnology Featuring Strained-Silicon

Scott E. Thompson, M Armstrong, C. Auth et al. · IEEE Electron Device Letters · 2004 · 513 citations

Engineering, Electrical Engineering, Materials Science +17

45nm High-k + metal gate strain-enhanced transistors

C. Auth, A. Cappellani, Jang‐Soo Chun et al. · 2008 · 204 citations

Engineering, Computer Engineering, Electrical Engineering +17