Electrical and Electronic Engineering · 2013 · 17 citations · 17 references
EngineeringElectrical EngineeringMaterials ScienceElectronic MaterialsMicroelectronicsSemiconductor DevicesDevice CharacterizationDevice ModelingDevice ReliabilityDevice SimulationReliability ModelingSemiconductor ReliabilityAging CharacterizationDevice DegradationGate LeakageGate Leakage CurrentLeakage CurrentLeakage Current ModelingReliability DegradationReliability Simulation
In this paper we present an empirical preliminary model able to simulate the degradation with time in the gate leakage current in GaN HEMT devices. The model is based on extensive reverse and forward current measurements, carried out on a wide range of different device designs and under different bias, performed over aged transistors by III-V Lab (Alcatel-Thales) within the European KORRIGAN. A closed form expression for the reverse gate current, depending on time, as well as the expression parameters extraction procedure are presented. The experimental and simulated results presented illustrate the validity of the model as well as itâs usefulness in reliability studies.
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