2013 · 27 citations · 7 references
EngineeringElectrical EngineeringMaterials ScienceMicroelectronicsSemiconductor DevicesSemiconductor MaterialsComplementary Metal-oxide-semiconductor TechnologyIii-v SemiconductorsIntegrated Circuit DesignP-n JunctionsSemiconductor Thin FilmsThin-film TransistorsCmos Fabrication ProcessesCurrentsDigital Logic CircuitsFabricationMetal GatesNear-threshold VoltageThree-dimensional IntegrationThreshold Voltage
A sequential layered integration technology that can fabricate 3D stackable epi-like Si FETs with and without metal back gate (MBG) under sub-400°C are proposed in this article. With laser crystallized epi-like Si and CMP thinning processes for channel fabrication, 3D stackable ultra thin body (UTB) n/p-MOSFETs with low-subthreshold swings (88 and 121 mV/dec.) and high on-currents (121 and 62 μA/μm) are demonstrated. With additional metal back gate structure, UTB devices can be desirably operated in a positive or negative threshold voltage range with γ values of 0.51 (n-MOSFETs) and 0.56 (p-MOSFETs) for favoring its applications in 3D logic circuits. In addition, such thin and high quality channel and metal back gate scheme is not only promising for conventional p-n junction device but also junctionless (JL) scheme, which can simplify the fabrication and achieve further scaling.
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Advances, challenges and opportunities in 3D CMOS sequential integration
P. Batude, M. Vinet, B. Prévitali et al. · 2011 · 148 citations · Full text
World's first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS
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Engineering, Computer Engineering, Electrical Engineering +16
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