IEEE Transactions on Electron Devices · 1988 · 19 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDevice CharacterizationDevice ModelingDevice SimulationIntegrated Circuit DesignTiming AnalysisCurrentsHigh-temperature Device OperationHigh-temperature ElectronicsLatch DesignSilicon WafersTemperature EffectsTemperature SensitivityThermal Effects In Integrated Circuits
A simple worst-case analytical model of holding currents and an empirical model of trigger currents are reported and shown to agree with experimental measurements in the range of 25-225 degrees C. Whereas standard bulk CMOS inverters and ring oscillators are invariably found to latchup near 125 degrees C, their counterparts built on epitaxial wafers remain latchup free up to at least 250 degrees C. These results add to an ongoing systematic effort to model high-temperature effects in integrated MOS technologies and provide worst case latchup information in the commercial temperature range and beyond.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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F.S. Shoucair, Wei Hwang, Prem C. Jain · IEEE Transactions on Components Hybrids and Manufacturing Technology · 1984 · 29 citations