2007 · 18 citations · 2 references
EngineeringElectrical EngineeringMaterials ScienceElectronic MaterialsMicroelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDevice ModelingIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsOxide SemiconductorsCmos Fabrication ProcessesLow-voltage Cmos DesignMetal Gates
A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> values of plusmn 0.25 V and unstrained I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DSAT</sub> of 1035/500 muA/mum for nMOS/pMOS at I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> =100nA/mum and |V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> |=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only activation anneal to maintain band-edge EWF and minimal EOT re-growth. The laser-only anneal further results in improved L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> scaling of 15 nm and a 2 Aring T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">INV</sub> reduction over the spike reference.
2
Fermi Pinning-Induced Thermal Instability of Metal-Gate Work Functions
H.Y. Yu, C. Ren, Yee‐Chia Yeo et al. · IEEE Electron Device Letters · 2004 · 131 citations