Silicon-gate n-well CMOS process by full ion-implantation technology

Abstract

A silicon-gate n-well CMOS process for an application of digital circuits operated by TTL compatible supply voltage was developed. Full ion-implantation technology, a new photolithography technique, n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -doped polysilicon gate which contain no boron impurities, and thin gate oxide of 65 nm can realize CMOS circuits of 2-µm gate length. Average impurity concentrations measured from substrate bias effect of MOSFET's and junction depth are in good agreement with those expected from impurity profiles calculated by a simple diffusion theory. So, the process design for CMOS circuits operated by any supply voltage is possible, by adjusting threshold voltages. The process can easily be extended to n-MOS/CMOS process (E/D MOS and CMOS on the same chip), if a photomask to fabricate depletion-type n-MOSFET's is provided.