T. Masuhara - Concepedia

Author

T. Masuhara

Hitachi (Japan)

Also Known As

T. Masuhara, Toshiaki Masuhara

Publications

799

Citations

H-Index

Concepts

All Affiliations

Hitachi (Japan)Musashi University

About

T. Masuhara is an author at Hitachi (Japan) specializing in microelectronics, electrical engineering, and engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	15	25	609
2	Electrical Engineering	15	24	596
3	Computer Engineering	13	17	414
4	Applied Physics	8	8	289
5	Health Sciences	1	1	13

T. Masuhara

Publications

637

Citations

H-Index

Page 1

	Year	Citations
Operation of bulk CMOS devices at very low temperatures H. Hanamura, Masashi Aoki, T. Masuhara, IEEE Journal of Solid-State Circuits Low-power ElectronicsHardware SecurityElectrical EngineeringLow TemperaturesVlsi Design	1986	101
Performance and hot-carrier effects of small CRYO-CMOS devices Masahiro Aoki, S. Hanamura, T. Masuhara, IEEE Transactions on Electron Devices Low-power ElectronicsElectrical EngineeringSubmicrometer Cmos DevicesLow TemperaturesEngineering	1987	77
A 20ns 64K CMOS SRAM O. Minato, T. Masuhara, Takeshi Sasaki, Hardware SecurityElectrical EngineeringMemory ArchitectureCmos SramVlsi Design	1984	34
A high-speed, low-power Hi-CMOS 4K static RAM T. Masuhara, O. Minato, Takeshi Sasaki, Low-power ElectronicsHardware SecurityElectrical EngineeringEngineeringComputer Architecture	1978	33
A high-performance N-channel MOSLSI using depletion-type load elements T. Masuhara, M. Nagata, N. Hashimoto IEEE Journal of Solid-State Circuits Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignCircuit System	1972	33
A precise MOSFET model for low-voltage circuits T. Masuhara, J. Etoh, M. Nagata IEEE Transactions on Electron Devices Device ModelingSaturation RegionsElectrical EngineeringEngineeringNanoelectronics	1974	31
Low-temperature CMOS 8 &#215; 8 bit multipliers with sub-10-ns speeds S. Hanamura, Masashi Aoki, T. Masuhara, IEEE Transactions on Electron Devices	1987	28
A soft error rate model for MOS dynamic RAM's T. Toyabe, Takashi Shinoda, Masakazu Aoki, IEEE Transactions on Electron Devices Hardware SecurityElectrical EngineeringAlpha EnergyEngineeringHardware Reliability	1982	27
Operation of Bulk CMOS Devices at Very Low Temperatures S. Hanamura, Masashi Aoki, T. Masuhara, Symposium on VLSI Technology Low-power ElectronicsElectrical EngineeringEngineeringBias Temperature InstabilityApplied Physics	1983	26
A Soft Error Rate Model for MOS Dynamic RAM's T. Toyabe, Takashi Shinoda, Masakazu Aoki, IEEE Journal of Solid-State Circuits Hardware SecurityElectrical EngineeringAlpha EnergyEngineeringHardware Reliability	1982	21

Page 1