Operation of bulk CMOS devices at very low temperatures

Abstract

Low-temperature (77K, 4.2K) operation is proposed for bulk CMOS devices to be used in superfast VLSI applications. Symmetrical variation of the parameters of both n-channel and p-channel MOSFETs with respect to the temperature and latch-up immunity makes CMOS a very promising device technology at low temperatures. To demonstrate the performance advantage of circuit operation at low temperatures, inverter chains and 16-kb static random-access memories (RAMs) with 2-/spl mu/m gate length were measured. Average propagation delay for an inverter chain has been reduced to 175 ps (77K) and 104 ps (4.2K) from 296 ps at 300K without sacrificing power dissipation. The power-delay product is less 1 fJ, which is the smallest for silicon devices reported to date. The chip select-access time of the RAM has been reduced to 14.3 ns (77K) from 24 ns (300K).