Operation of bulk CMOS devices at very low temperatures

H. Hanamura, Masashi Aoki, T. Masuhara, +3

IEEE Journal of Solid-State Circuits

Low-power ElectronicsHardware SecurityElectrical EngineeringLow TemperaturesVlsi Design +12

A 20ns 64K CMOS SRAM

O. Minato, T. Masuhara, Takeshi Sasaki, +2

Hardware SecurityElectrical EngineeringMemory ArchitectureCmos SramVlsi Design +12

A high-speed, low-power Hi-CMOS 4K static RAM

T. Masuhara, O. Minato, Takeshi Sasaki, +3

Low-power ElectronicsHardware SecurityElectrical EngineeringEngineeringComputer Architecture +4

Low-temperature CMOS 8 × 8 bit multipliers with sub-10-ns speeds

S. Hanamura, Masashi Aoki, T. Masuhara, +3

IEEE Transactions on Electron Devices

Operation of Bulk CMOS Devices at Very Low Temperatures

S. Hanamura, Masashi Aoki, T. Masuhara, +3

Symposium on VLSI Technology

Low-power ElectronicsElectrical EngineeringEngineeringBias Temperature InstabilityApplied Physics +4

A HI-CMOSII 8K × 8b static RAM

O. Minato, T. Masuhara, Takeshi Sasaki, +6

Hardware SecurityElectrical EngineeringMemory ArchitectureEngineeringAdvanced Packaging (Semiconductors) +7

A Hi-CMOSII 8Kx8 bit static RAM

O. Minato, T. Masuhara, Takeshi Sasaki, +5

IEEE Journal of Solid-State Circuits

Hardware SecurityElectrical EngineeringDouble Polysilicon TechnologyEngineeringVlsi Design +9

Grooved Gate MOSFET

Shigeru Nishimatsu, Yoshifumi Kawamoto, Hiroo Masuda, +2

Japanese Journal of Applied Physics

Device ModelingElectrical EngineeringDrain Junction DepthEngineeringNanoelectronics +8

HI-CMOSII 4K static RAM

O. Minato, T. Masuhara, Takeshi Sasaki, +2

Low-power ElectronicsElectrical EngineeringGate LengthEngineeringVlsi Design +7

A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current

K. Sasaki, Koichiro Ishibashi, K. Shimohigashi, +7

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignWord-decoder Architecture +9