Publication | Closed Access
A 20ns 64K CMOS SRAM
34
Citations
2
References
1984
Year
Unknown Venue
Hardware SecurityElectrical EngineeringMemory ArchitectureCmos SramVlsi DesignEngineeringEmerging Memory TechnologyComputer EngineeringComputer ArchitecturePower DissipationMemory DevicesSemiconductor MemoryGate Mos TransistorsP-well/bipolar TechnologyMicroelectronicsMemory ReliabilityMulti-channel Memory Architecture
A 19.0mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 64K×1 SRAM utilizing pulsed-word-line technique, P-well/bipolar technology, and 1.3μm gate MOS transistors, will be described. The RAM has typical address access time of 20ns and power dissipation of 70mW at 1 MHz cycle time.
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