Intrinsic leakage in low power deep submicron CMOS ICs

Abstract

The large leakage currents in deep submicron transistors threaten future products and established quality manufacturing techniques. These include the ability to manufacture low power and battery operated products, and the ability to perform I/sub DDQ/ sensitive measurements with the significant ensuing benefits to test, reliability, and failure analysis. This paper reports transistor intrinsic leakage reduction as functions of bias point, temperature, source-well backbiasing, and lowered power supply (V/sub DD/). These device properties are applied to a test application that combines I/sub DDQ/ and F/sub MAX/ to establish a 2-parameter limit for distinguishing intrinsic and extrinsic (defect) leakages in microprocessors with high background I/sub DDQ/ leakage.