Capacitance Expressions and Electrical Characterization of Tapered Through- Silicon Vias for 3-D ICs

Abstract

Closed-form expressions of the parasitic insulator capacitance and the substrate capacitance for tapered through-silicon vias (T-TSVs) are proposed. The expressions are suitable for TSVs with high aspect ratio (thin and long). The maximum percentage errors between the calculated and simulated results for the insulator capacitance and the substrate capacitance are 1.86% and 3.75%, respectively. Then the equivalent circuit model of the T-TSV signal-ground pair is established and validated by comparison with the full-wave simulation results. Furthermore, the electrical characteristics of the T-TSV are evaluated with the proposed expressions. The results indicate that the T-TSV has longer latency and less crosstalk than the cylindrical TSVs.