Jun So Pak

High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)

Joohee Kim, Jun So Pak, Jonghyun Cho et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 2011 · 479 citations

Engineering, Vlsi Design, Scalable Model +17

Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring

Jonghyun Cho, Eakhwan Song, Ki-Hyun Yoon et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 2011 · 164 citations

Engineering, Through-silicon Via, Interconnect (Integrated Circuits) +16

PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models

Jun So Pak, Joohee Kim, Jonghyun Cho et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 2011 · 128 citations

Engineering, Chip-pdn Models, Power Electronics +16

Chip-Package Hierarchical Power Distribution Network Modeling and Analysis Based on a Segmentation Method

Jaemin Kim, Woojin Lee, Yujeong Shim et al. · IEEE Transactions on Advanced Packaging · 2010 · 98 citations

Power Engineering, Engineering, Power Optimization (Eda) +20

Electrical characterization of trough silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation

Jun So Pak, Chunghyun Ryu, Joungho Kim · 2007 · 97 citations

Engineering, Integrated Circuits, Silicon On Insulator +19