Three-dimensional Device Scaling

Three-Dimensional Device Scaling is a semiconductor device scaling strategy that extends miniaturization beyond planar dimensions by vertically integrating multiple layers or stacks of transistors, thereby increasing device density and performance while mitigating short-channel effects inherent in traditional two-dimensional scaling.

116

Publications

5K

Citations

774

Authors

105

Institutions

Publications per year

2017–2026

40

Authors

774

  1. JR
    Julien Ryckaert

    IMEC, Belgium

    5 publications · 238 citations

    6

    h-index

  2. HL
    Hang-Ting Lue

    Macronix International (Taiwan), Taiwan

    5 publications · 188 citations

    5

    h-index

  3. NC
    Nadine Collaert

    IMEC, Belgium

    4 publications · 426 citations

    4

    h-index

  4. YH
    Yi‐Hsuan Hsiao

    Changhua Christian Hospital, Taiwan

    4 publications · 174 citations

    4

    h-index

  5. CL
    Chih-Yuan Lu

    Macronix International (Taiwan), Taiwan

    4 publications · 174 citations

    4

    h-index

1–5 of 774

Venues

  1. IEEE Transactions on Electron Devices

    8 publications · 666 citations

    8

    h-index

  2. IEEE Electron Device Letters

    3 publications · 100 citations

    4

    h-index

  3. IBM Journal of Research and Development

    2 publications · 234 citations

    2

    h-index

  4. European Solid-State Device Research Conference

    Conference · 2 publications · 48 citations

    2

    h-index

  5. Applied Physics Letters

    2 publications · 86 citations

    2

    h-index

1–5