Three-dimensional Device Scaling
Three-Dimensional Device Scaling is a semiconductor device scaling strategy that extends miniaturization beyond planar dimensions by vertically integrating multiple layers or stacks of transistors, thereby increasing device density and performance while mitigating short-channel effects inherent in traditional two-dimensional scaling.
116
Publications
5K
Citations
774
Authors
105
Institutions
Publications per year
2017–2026
40
Parents
116
Perspective: New process technologies required for future devices and scaling
Robert D. Clark, Kandabara Tapily, K.H. Yu et al. · APL Materials · 2018 · 192 citations · Full text
Recent Progress on 3D NAND Flash Technologies
Akira Goda · Electronics · 2021 · 152 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +16
First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers
S. Subramanian, M. Reza Hosseini, T. Chiarella et al. · 2020 · 119 citations
1–5 of 116
774
6
h-index
5
h-index
4
h-index
4
h-index
4
h-index
1–5 of 774
105
IMEC
Leuven, Belgium
11 h-index
132 publications
7K citations
Samsung (South Korea)
Seoul, South Korea
8 h-index
175 publications
11.5K citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
6 h-index
36 publications
2.3K citations
Micron (United States)
Boise, United States
6 h-index
10 publications
562 citations
Intel (United States)
Santa Clara, United States
5 h-index
32 publications
3.5K citations
Macronix International (Taiwan)
Hsinchu, Taiwan
5 h-index
60 publications
1.9K citations
Georgia Institute of Technology
Atlanta, United States
5 h-index
9 publications
274 citations
Toshiba (Japan)
Tokyo, Japan
4 h-index
12 publications
763 citations
1–8 of 105
8 publications · 666 citations
8
h-index
3 publications · 100 citations
4
h-index
2 publications · 234 citations
2
h-index
Conference · 2 publications · 48 citations
2
h-index
2 publications · 86 citations
2
h-index
1–5