Yee-Chia Yeo

Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

Yee-Chia Yeo, Qiang Lu, P. Ranade et al. · IEEE Electron Device Letters · 2001 · 109 citations

Materials Engineering, Gate Dielectric Stack, Electrical Engineering +13

Sub-0.1-eV Effective Schottky-Barrier Height for NiSi on n-Type Si (100) Using Antimony Segregation

Hoong-Shing Wong, Lap Chan, Ganesh Samudra et al. · IEEE Electron Device Letters · 2007 · 45 citations

Semiconductors, Semiconductor Technology, Electrical Engineering +14

Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel

Yee-Chia Yeo, Vivek Subramanian, J. Kedzierski et al. · IEEE Transactions on Electron Devices · 2002 · 34 citations

Electrical Engineering, Semiconductor Device, Thin-body Mos Transistor +13

Drive-Current Enhancement in FinFETs Using Gate-Induced Stress

Kian-Ming Tan, Tsung-Yang Liow, R.T.P. Lee et al. · IEEE Electron Device Letters · 2006 · 16 citations

Materials Engineering, Electrical Engineering, Si Channel +11

Thermally robust TaTb/sub x/N metal gate electrode for n-MOSFETs applications

Chao Ren, H.Y. Yu, X.P. Wang et al. · IEEE Electron Device Letters · 2005 · 11 citations

Materials Engineering, Materials Science, Electrical Engineering +13