A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay

T. Saeki, Y. Nakaoka, Masafumi Fujita, +29

IEEE Journal of Solid-State Circuits

System On Chip256-Mb SdramVlsi DesignEngineeringChip Size Reduction +13

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A. Tanabe, T. Takeshima, Hiroki Koike, +16

IEEE Journal of Solid-State Circuits

EngineeringEmerging Memory TechnologyMem TestingComputer ArchitectureOpen Bit-line Readout +14

Impact of gate-induced drain leakage current on the tail distribution of DRAM data retention time

K. Saino, S. Horiba, Shiro Uchiyama, +7

Hardware SecurityNon-volatile MemoryElectrical EngineeringTail-mode BitsEngineering +10

A 1-gb/s/pin 512-mb ddrii sdram using a digital dll and a slew-rate-controlled output buffer

T. Matano, Y. Takai, T. Takahashi, +12

IEEE Journal of Solid-State Circuits

Slew-rate-controlled Output BufferEngineeringVlsi DesignAnalog-to-digital ConverterData Converter +13

A 7.68 GIPS 3.84 GB/s 1W parallel image processing RAM integrating a 16 Mb DRAM and 128 processors

Y. Aimoto, Tsukasa Kimura, Y. Yabe, +9

Non-volatile MemoryImage ProcessingEngineeringHardware AccelerationSingle Chip +12

A 4-level storage 4 Gb DRAM

T. Murotani, I. Naritake, T. Matano, +8

Hardware SecurityFile Application DramsElectrical EngineeringEngineeringChip Size Reduction +11

A 1-Gb DRAM for file applications

Tadahiko Sugibayashi, I. Naritake, Satoru Utsugi, +12

IEEE Journal of Solid-State Circuits

Non-volatile MemoryElectrical EngineeringCell SizeEngineeringComputer Engineering +9

A 1 Gb DRAM for file applications

Tadahiko Sugibayashi, I. Naritake, Satoru Utsugi, +12

Hardware SecurityNon-volatile MemoryElectrical EngineeringLarge Capacity DramsEngineering +10

A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM

T. Takeshima, Midori Takada, Hiroki Koike, +10

IEEE Journal of Solid-State Circuits

EngineeringMemory DesignEmerging Memory TechnologyMem TestingComputer Architecture +18

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

T. Matano, Mario Morino, M. Nakamura, +12

Slew-rate-controlled Output BufferEngineeringVlsi DesignAnalog-to-digital ConverterData Converter +12