Y. Toyoshima

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology

J. Mori, M. Nagamatsu, M. Hirano et al. · IEEE Journal of Solid-State Circuits · 1991 · 98 citations

Electrical Engineering, Engineering, Vlsi Design +12

Analysis of hot-carrier-induced degradation mode on pMOSFET's

F. Matsuoka, Hiroshi Iwai, H. Hayashida et al. · IEEE Transactions on Electron Devices · 1990 · 67 citations

Buried-channel Pmosfets, Electrical Engineering, Engineering +15

Analysis on gate-oxide thickness dependence of hot-carrier-induced degradation in thin-gate oxide nMOSFET's

Y. Toyoshima, Hiroshi Iwai, F. Matsuoka et al. · IEEE Transactions on Electron Devices · 1990 · 66 citations

Device Modeling, Gate-oxide Thickness Dependence, Electrical Engineering +12

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

E. Leobandung, H. Nayakama, D. Mocuta et al. · 2005 · 65 citations

Electrical Engineering, Engineering, Vlsi Design +15

1.5-nm Gate oxide CMOS on [110] surface-oriented Si substrate

H.S. Momose, T. Ohguro, Kazunobu Kojima et al. · IEEE Transactions on Electron Devices · 2003 · 57 citations

Electrical Engineering, Engineering, Rf Semiconductor +11