Analysis of hot-carrier-induced degradation mode on pMOSFET's

Abstract

Hot-carrier-induced degradation surface-channel (p/sup +/ polysilicon gate) and buried-channel (n/sup +/ polysilicon gate) pMOSFETs is discussed. In the shallow gate bias region, a hot-carrier degradation mode by drain avalanche hot hole injection was found for the surface-channel pMOSFETs. Trapped holes and interface state generation, which were not observed in the buried-channel pMOSFETs, were detected. In this gate bias region, the degradation for the surface-channel structure is smaller than that for the buried-channel structure. Three reasons for the smaller degradation in the surface-channel structure are discussed. The deep-gate bias region was also investigated. In this region, an interface-state generation mode without the threshold-voltage shift was found for both surface- and buried-channel pMOSFETs. This interface state generation is caused by channel hot hole injection.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>