A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology

J. Mori, M. Nagamatsu, M. Hirano, +6

IEEE Journal of Solid-State Circuits

Electrical EngineeringEngineeringVlsi DesignMultiplication SpeedB Parallel +10

Radiation-Induced Interface States of Poly-Si Gate MOS Capacitors Using Low Temperature Gate Oxidation

Kiyomi Naruke, Masahiro Yoshida, K. Maeguchi, +1

IEEE Transactions on Nuclear Science

Electrical EngineeringEngineeringBias Temperature InstabilityApplied PhysicsGate Oxidation Temperature +6

Analysis of hot-carrier-induced degradation mode on pMOSFET's

F. Matsuoka, Hiroshi Iwai, H. Hayashida, +3

IEEE Transactions on Electron Devices

Buried-channel PmosfetsElectrical EngineeringEngineeringHot-carrier-induced Degradation ModeNanoelectronics +13

Analysis on gate-oxide thickness dependence of hot-carrier-induced degradation in thin-gate oxide nMOSFET's

Y. Toyoshima, Hiroshi Iwai, F. Matsuoka, +3

IEEE Transactions on Electron Devices

Device ModelingGate-oxide Thickness DependenceElectrical EngineeringThinner GateEngineering +10

A single-chip MPEG2 video decoder LSI

T. Demura, T. Oto, K. Kitagaki, +16

Mpeg1 StandardEngineeringImage CodingImage CompressionMultimedia Signal Processing +7

Interface state generation under long-term positive-bias temperature stress for a p/sup +/ poly gate MOS structure

Y. Hiruta, Hiroshi Iwai, F. Matsuoka, +3

IEEE Transactions on Electron Devices

Semiconductor TechnologyElectrical EngineeringSemiconductor DeviceEngineeringStress-induced Leakage Current +12

Embedded DRAM technologies

H. Ishiuchi, Takeshi Yoshida, H. Takato, +6

Hardware SecurityNon-volatile MemoryElectrical EngineeringEngineeringEmerging Memory Technology +11

Electromigration reliability for a tungsten-filled via hole structure

F. Matsuoka, Hiroshi Iwai, K. Hama, +5

IEEE Transactions on Electron Devices

Materials EngineeringMaterials ScienceElectrical EngineeringElectromigration TechniqueEngineering +10

Dopant redistribution in dual gate W-polycide CMOS and its improvement by RTA

H. Hayashida, Y. Toyoshima, Y. Suizu, +3

Symposium on VLSI Technology

Electrical EngineeringEngineeringBias Temperature InstabilityDopant RedistributionMicroelectronics +1

Increase of resistance to hot carriers in thin oxide MOSFETS

Masahiro Yoshida, Daisuke Tohyama, K. Maeguchi, +1

Device ModelingMaterials ScienceElectrical EngineeringEngineeringStress-induced Leakage Current +9