Novel locally strained channel technique for high performance 55nm CMOS

K. Ota, Kenya Sugihara, H. Sayama, +5

Low-power ElectronicsElectrical EngineeringChannel TechniqueEngineeringVlsi Design +10

Smallest V<inf>th</inf> variability achieved by intrinsic silicon on thin BOX (SOTB) CMOS with single metal gate

Yukinori Morita, Ryuta Tsuchiya, Takashi Ishigaki, +7

EngineeringThin BoxSilicon On InsulatorSemiconductor DeviceSmallest V +14

Ultra-low power and ultra-low voltage devices and circuits for IoT applications

Toshiro Hiramoto, Ken Takeuchi, T. Mizutani, +10

EngineeringUltra-low Voltage DevicesHigh Voltage EngineeringElectronic EngineeringInternet Of Things +15

Three-dimensional topography simulation model: etching and lithography

M. Fujinaga, N. Kotani, T. Kunikiyo, +3

IEEE Transactions on Electron Devices

EngineeringElectron-beam LithographyMicroscopy3D ModelingComputer-aided Design +15

Source-to-drain breakdown voltage improvement in ultrathin-film SOI MOSFET's using a gate-overlapped LDD structure

Yutaro Yamaguchi, T. Iwamatsu, H.-O. Joachim, +4

IEEE Transactions on Electron Devices

Semiconductor TechnologyElectrical EngineeringEngineeringHigh Voltage EngineeringBias Temperature Instability +8

Effect of >100< channel direction for high performance SCE immune pMOSFET with less than 0.15 μm gate length

H. Sayama, Y. Nishida, H. Oda, +6

Low-power ElectronicsElectrical EngineeringCurrent DrivabilityEngineeringHigh Performance Sce +9

Novel SOI wafer engineering using low stress and high mobility CMOSFET with >100<-channel for embedded RF/analog applications

Takeru Matsumoto, S. Maeda, Hung Dang, +10

Low-power ElectronicsElectrical EngineeringEngineeringRf SemiconductorAdvanced Packaging (Semiconductors) +12

Controllable Inverter Delay and Suppressing V<inf>th</inf> Fluctuation Technology in Silicon on Thin BOX Featuring Dual Back-Gate Bias Architecture

Ryuta Tsuchiya, Takashi Ishigaki, Yusuke Morita, +8

Low-power ElectronicsElectrical EngineeringEngineeringThin BoxSotb Device Design +10

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, +22

Low-power ElectronicsPerpetuum Mobile 32BitElectrical EngineeringPower-aware ComputingThin Buried Oxide +10

Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation

Y. Yamamoto, Hideki Makiyama, Takaaki Tsunomura, +6