Novel locally strained channel technique for high performance 55nm CMOS

Abstract

A novel local strained channel (LSC) MOSFET has been fabricated by a stress control technique utilizing a strained poly silicon gate electrode. The residual compressive stress in arsenic (As) implanted polysilicon is induced by high temperature annealing of CVD SiO/sub 2/ cap with high tensile stress. On the other hand, boron (B) implanted poly silicon is free from stress. As a result, the only n-channel region is locally strained by the strained polysilicon electrode. The drain current of LSC nFETs is improved 15% compared to that of the conventional nFET without the degradation of pFET drain current. High performance 55nm CMOSFET is realized by simple process for LSC-structure.