Discrete Dopant Effects on Statistical Variation of Random Telegraph Signal Magnitude

K. Sonoda, Kiyoshi Ishikawa, T. Eimori, +1

IEEE Transactions on Electron Devices

Discrete Dopant EffectsElectrical EngineeringEngineeringPhysicsStatistical Variation +5

Novel locally strained channel technique for high performance 55nm CMOS

K. Ota, Kenya Sugihara, H. Sayama, +5

Low-power ElectronicsElectrical EngineeringChannel TechniqueEngineeringVlsi Design +10

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

K. Suma, T. Tsuruda, Hideto Hidaka, +11

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringCmos/simox TechnologyData Retention TimeVlsi Design +10

Ultrathin poly(methylmethacrylate) resist films for microlithography

S. W. J. Kuan, C. W. Frank, Y. H. Yen Lee, +4

Journal of Vacuum Science & Technology B Microelectronics Processing and Phenomena

EngineeringElectron-beam LithographyThin Film Process TechnologyUltrathin PolyBeam Lithography +15

Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAM

Fukashi Morishita, K. Suma, Masakazu Hirose, +7

Hardware SecurityNon-volatile MemoryElectrical EngineeringCell TransistorEngineering +12

An elastic cross section model for use with Monte Carlo simulations of low energy electron scattering from high atomic number targets

R. Browning, T. Eimori, E. P. Traut, +2

Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena

Cross SectionLow Energy ElectronNuclear PhysicsEngineeringElectron Diffraction +21

Physical model of the PBTI and TDDB of la incorporated HfSiON gate dielectrics with pre-existing and stress-induced defects

Motoyuki Sato, Naoto Umezawa, J. Shimokawa, +16

EngineeringLa IncorporationDefect ToleranceSemiconductor DeviceOxygen Vacancy +17

A 34 ns 256 Mb DRAM with boosted sense-ground scheme

M. Asakura, T. Ohishi, M. Tsukude, +12

EngineeringMemory DesignEmerging Memory TechnologyComputer ArchitectureMulti-channel Memory Architecture +18

An experimental 256-Mb DRAM with boosted sense-ground scheme

M. Asakura, T. Ooishi, M. Tsukude, +8

IEEE Journal of Solid-State Circuits

Non-volatile MemoryEngineeringMemory DesignEmerging Memory TechnologyComputer Architecture +14

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique

K. Shimomura, H. Shimano, N. Sakashita, +10

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignHigh Speed +9