Rapid annealing and the anomalous diffusion of ion implanted boron into silicon

A. E. Michel, W. Rausch, Paul Ronsheim, +1

Applied Physics Letters

Decay TimeEngineeringSilicon On InsulatorSemiconductor DeviceSemiconductors +14

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

P. Agnello, T. Ivers, C. Warm, +77

EngineeringVlsi DesignEnhanced StrainPorous Low-k BeolIntegrated Circuits +19

Implantation damage and the anomalous transient diffusion of ion-implanted boron

A. E. Michel, W. Rausch, Paul Ronsheim

Applied Physics Letters

Point DefectsEngineeringImplantation DamagePoint Defect ClustersSilicon On Insulator +14

Partially-depleted SOI technology for digital logic

G. Shahidi, A. Ajmera, F. Assaderaghi, +8

Hardware SecurityElectrical EngineeringSoi TechnologyEngineeringVlsi Design +12

A 0.25 μm CMOS SOI technology and its application to 4 Mb SRAM

D. Schepis, F. Assaderaghi, D. S. Yee, +24

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignVlsi Architecture +8

A 7.9/5.5 psec room/low temperature SOI CMOS

F. Assaderaghi, W. Rausch, A. Ajmera, +8

Low-power ElectronicsRoom TemperatureElectrical EngineeringEngineeringVlsi Design +9

A high performance 90nm SOI technology with 0.992 μm/sup 2/ 6T-SRAM cell

Mukesh Khare, S.H. Ku, R. A. Donaton, +39

Low-power ElectronicsMaterials ScienceElectrical EngineeringHigh Performance 90NmSoi Technology +12

Mainstreaming of the SOI technology

G. Shahidi, Hellen Lo, M. Maloney, +18

EngineeringVlsi DesignComputer ArchitectureTechnology AssessmentSilicon On Insulator +24

Electrostatic discharge protection in silicon-on-insulator technology

Steven H. Voldman, David Hui, L. Warriner, +11

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignElectrostatic Discharge +12

Scalability of SOI technology into 0.13 μm 1.2 V CMOS generation

E. Leobandung, M. Sherony, J.W. Sleight, +8

Low-power ElectronicsElectrical EngineeringSoi TechnologyEngineeringVlsi Design +10