Ultrathin high-K gate stacks for advanced CMOS devices

E. P. Gusev, D. A. Buchanan, E. Cartier, +20

EngineeringVlsi DesignSilicon On InsulatorSemiconductor DeviceNanoelectronics +14

Optimization of the germanium preamorphization conditions for shallow-junction formation

Mehmet C. Öztürk, J. J. Wortman, C. M. Osburn, +5

IEEE Transactions on Electron Devices

Materials ScienceIon ImplantationEngineeringGermanium Preamorphization ConditionsApplied Physics +8

Elimination of end-of-range and mask edge lateral damage in Ge+ preamorphized, B+ implanted Si

A. Ajmera, G. A. Rozgonyi

Applied Physics Letters

Materials ScienceSemiconductor TechnologyIon ImplantationEngineeringBoron Profiles +10

High performance and low power transistors integrated in 65nm bulk CMOS technology

Zuying Luo, An Steegen, M. Eller, +38

Low-power ElectronicsLow Power ApplicationsElectrical EngineeringEngineeringVlsi Design +10

Partially-depleted SOI technology for digital logic

G. Shahidi, A. Ajmera, F. Assaderaghi, +8

Hardware SecurityElectrical EngineeringSoi TechnologyEngineeringVlsi Design +12

A 0.25 μm CMOS SOI technology and its application to 4 Mb SRAM

D. Schepis, F. Assaderaghi, D. S. Yee, +24

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignVlsi Architecture +8

80 nm polysilicon gated n-FETs with ultra-thin Al/sub 2/O/sub 3/ gate dielectric for ULSI applications

D. A. Buchanan, E. P. Gusev, E. Cartier, +16

Materials ScienceMaterials EngineeringElectrical EngineeringSemiconductor TechnologyEngineering +13

Point defect/dopant diffusion considerations following preamorphization of silicon via Si+ and Ge+ implantation

A. Ajmera, G. A. Rozgonyi, Richard B. Fair

Applied Physics Letters

Materials ScienceMaterials EngineeringIon ImplantationEngineeringCrystalline Defects +13

A 7.9/5.5 psec room/low temperature SOI CMOS

F. Assaderaghi, W. Rausch, A. Ajmera, +8

Low-power ElectronicsRoom TemperatureElectrical EngineeringEngineeringVlsi Design +9

65nm cmos technology for low power applications

An Steegen, R. Mo, R. Mann, +54

Low-power ElectronicsLow Power ApplicationsElectrical EngineeringLow Power TechnologyVlsi Design +11