Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

F. Assaderaghi, D. Sinitsky, S. Parke, +3

IEEE Transactions on Electron Devices

Low-power ElectronicsElectrical EngineeringStandard MosfetEngineeringVlsi Design +8

A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation

F. Assaderaghi, D. Sinitsky, S. Parke, +3

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignLower Bound +7

A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation

F. Assaderaghi, S. Parke, D. Sinitsky, +3

IEEE Electron Device Letters

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignApplied Physics +10

A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With <formula formulatype="inline"> <tex Notation="TeX">$< \pm \hbox{0.5-ppm}$</tex></formula> Frequency Stability and <formula formulatype="inline"><tex Notation="TeX">$< \hbox{1-ps}$</tex></formula> Integrated Jitter

Michael H. Perrott, J. Salvia, Fred S. Lee, +10

IEEE Journal of Solid-State Circuits

EngineeringOscillatorsAnalog DesignIntegrated CircuitsMicro-electromechanical System +15

The enhancement of gate-induced-drain-leakage (GIDL) current in short-channel SOI MOSFET and its application in measuring lateral bipolar current gain beta

J. Chen, F. Assaderaghi, P.K. Ko, +1

IEEE Electron Device Letters

Device ModelingShort-channel Soi MosfetElectrical EngineeringEngineeringShort-channel Soi Mosfets +7

Partially-depleted SOI technology for digital logic

G. Shahidi, A. Ajmera, F. Assaderaghi, +8

Hardware SecurityElectrical EngineeringSoi TechnologyEngineeringVlsi Design +12

Low jitter and temperature stable MEMS oscillators

Haechang Lee, Aaron Partridge, F. Assaderaghi

Electrical EngineeringLow JitterEngineeringPhysicsOscillators +12

Clocking and circuit design for a parallel I/O on a first-generation CELL processor

Ken Chang, Sudhakar Pamarti, Kambiz Kaviani, +10

EngineeringVlsi DesignAnalog DesignComputer ArchitectureProcessor Architecture +14

Recessed-channel structure for fabricating ultrathin SOI MOSFET with low series resistance

Mansun Chan, F. Assaderaghi, S. Parke, +2

IEEE Electron Device Letters

Materials ScienceLow Series ResistanceElectrical EngineeringSemiconductor TechnologyEngineering +12

A 0.25 μm CMOS SOI technology and its application to 4 Mb SRAM

D. Schepis, F. Assaderaghi, D. S. Yee, +24

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignVlsi Architecture +8