Atomic Layer Deposition of Ruthenium with TiN Interface for Sub-10 nm Advanced Interconnects beyond Copper

Liang Wen, Philippe Roussel, Olalla Varela Pedreira, +18

ACS Applied Materials & Interfaces

Scalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology

Eric Beyne, Soon-Wook Kim, Lan Peng, +9

EngineeringIntegrated CircuitsSilicon On InsulatorInterconnect (Integrated Circuits)Wafer Scale Processing +14

Novel Cu/SiCN surface topography control for 1 μm pitch hybrid wafer-to-wafer bonding

Soon-Wook Kim, Ferenc Fodor, N. Heylen, +5

EngineeringMechanical EngineeringInterconnect (Integrated Circuits)Wafer Scale ProcessingNanoelectronics +16

Influence of absorbed water components on SiOCH low-k reliability

Yunlong Li, Ivan Ciofi, L. Carbonell, +6

Journal of Applied Physics

Absorbed Water ComponentsReliability EngineeringChemisorbed Water ComponentEngineeringEnvironmental Engineering +7

A Thermally Stable and High-Performance 90-nm ${\rm Al}_{2}{\rm O}_{3}\backslash{\rm Cu}$-Based 1T1R CBRAM Cell

Attilio Belmonte, Woo‐Sik Kim, Boon Teik Chan, +5

IEEE Transactions on Electron Devices

Aluminium NitrideEngineeringVlsi DesignCell IntegrityEmerging Memory Technology +16

Ruthenium metallization for advanced interconnects

Liang Wen, Christoph Adelmann, Olalla Varela Pedreira, +10

Materials EngineeringMaterials ScienceElectrical EngineeringElectromigration TechniqueEngineering +12

Ultra-Fine Pitch 3D Integration Using Face-to-Face Hybrid Wafer Bonding Combined with a Via-Middle Through-Silicon-Via Process

Soon-Wook Kim, Mikael Detalle, Lan Peng, +6

EngineeringIntegrated CircuitsInterconnect (Integrated Circuits)Wafer Scale ProcessingAdvanced Packaging (Semiconductors) +18

Geometry Effect on Impurity Incorporation and Grain Growth in Narrow Copper Lines

W. Zhang, S. H. Brongersma, N. Heylen, +3

Journal of The Electrochemical Society

EngineeringVacuum DeviceInterconnect (Integrated Circuits)Copper Grain GrowthMaterials Science +14

Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers

A. Redolfi, Dimitrios Velenis, Sarasvathi Thangaraju, +17

EngineeringSilicon ViasIntegrated CircuitsInterconnect (Integrated Circuits)Cmos Flow +16

High-Aspect-Ratio Ruthenium Lines for Buried Power Rail

Anshul Gupta, Shreya Kundu, Lieve Teugels, +9

Materials ScienceLow-power ElectronicsElectrical EngineeringEngineeringPower Rail +12