Implementation of templated DSA for via layer patterning at the 7nm node

Roel Gronheid, Jan Doise, Joost Bekaert, +9

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

EngineeringMechanical EngineeringComputer ArchitecturePattern TransferComputer-aided Design +18

First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

S. Subramanian, M. Reza Hosseini, T. Chiarella, +29

EngineeringN14 PlatformInterconnect (Integrated Circuits)Complementary FetPhysical Design (Electronics) +14

A Thermally Stable and High-Performance 90-nm ${\rm Al}_{2}{\rm O}_{3}\backslash{\rm Cu}$-Based 1T1R CBRAM Cell

Attilio Belmonte, Woo‐Sik Kim, Boon Teik Chan, +5

IEEE Transactions on Electron Devices

Aluminium NitrideEngineeringVlsi DesignCell IntegrityEmerging Memory Technology +16

Area-Selective Atomic Layer Deposition of TiN, TiO₂, and HfO₂ on Silicon Nitride with inhibition on Amorphous Carbon

Eric C. Stevens, Yoann Tomczak, Boon Teik Chan, +3

Chemistry of Materials

Hfo2 Thin FilmsEngineeringThin Film Process TechnologyChemical DepositionThin Film Processing +14

Insight into Selective Surface Reactions of Dimethylamino-trimethylsilane for Area-Selective Deposition of Metal, Nitride, and Oxide

Job Soethoudt, Yoann Tomczak, Ben Meynaerts, +2

The Journal of Physical Chemistry C

Defect reduction and defect stability in IMEC's 14nm half-pitch chemo-epitaxy DSA flow

Roel Gronheid, Paulina Rincon Delgadillo, Hari Pathangi, +13

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

EngineeringDsa ProgramDefect StabilityDefect TolerancePolymers +19

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning

Hans Mertens, Maryam Hosseini, T. Chiarella, +37

Electrical EngineeringEngineeringVlsi DesignMicrofabricationNanotechnology +12

CFET SRAM DTCO, Interconnect Guideline, and Benchmark for CMOS Scaling

Hsiao-Hsuan Liu, Shairfe Muhammad Salahuddin, Boon Teik Chan, +6

IEEE Transactions on Electron Devices

Electrical EngineeringStacked ArchitectureEngineeringVlsi DesignTechnology Scaling +11

Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond

R. Ritzenthaler, Hans Mertens, Geert Eneman, +15

2021 IEEE International Electron Devices Meeting (IEDM)

EngineeringElectrical PerformanceIntegrated CircuitsNanocomputingInterconnect (Integrated Circuits) +17

Defect mitigation and root cause studies in 14 nm half-pitch chemo-epitaxy directed self-assembly LiNe flow

Hari Pathangi, Boon Teik Chan, Hareen Bayana, +15

Journal of Micro/Nanolithography MEMS and MOEMS

Materials ScienceMaterials EngineeringDefect ToleranceDsa MaterialsEngineering +12