Characterization and integration of a CVD porous SiOCH (k<2.5) with enhanced mechanical properties for 65 nm CMOS interconnects and below

L.L. Chapelon, V. Arnal, M. Broekaart, +3

Microelectronic Engineering

Materials ScienceElectrical EngineeringEngineeringAdvanced Packaging (Semiconductors)Enhanced Mechanical Properties +11

Advanced Cu interconnects using air gaps

L.G. Gosset, A. Farcy, J. de Pontcharra, +12

Microelectronic Engineering

3D Ic ArchitectureElectrical EngineeringEngineeringAdvanced Packaging (Semiconductors)Nanoelectronics +5

Impact of the Cu-based substrates and catalyst deposition techniques on carbon nanotube growth at low temperature by PECVD

M. Dubosc, S. Casimirius, Marie‐Paule Besland, +7

Microelectronic Engineering

Materials ScienceChemical EngineeringEngineeringCarbon-based MaterialNanomaterials +8

Influence of SiH4 process step on physical and electrical properties of advanced copper interconnects

S. Chhun, L.G. Gosset, N. Casanova, +7

Microelectronic Engineering

Materials ScienceElectrical EngineeringElectromigration TechniqueEngineeringNanoelectronics +7

Impact of patterning and ashing on electrical properties and reliability of interconnects in a porous SiOCH ultra low-k dielectric material

M. Aimadeddine, V. Arnal, A. Farcy, +7

Microelectronic Engineering

Materials EngineeringMaterials ScienceElectrical EngineeringEngineeringApplied Physics +9

Sidewall restoration of porous ultra low-k dielectrics for sub-45nm technology nodes

H. Chaabouni, L.L. Chapelon, M. Aimadeddine, +9

Microelectronic Engineering

Materials ScienceElectrical EngineeringEngineeringNanoelectronicsApplied Physics +7

Residue growth on metallic-hard mask after dielectric etching in fluorocarbon-based plasmas. I. Mechanisms

N. Possémé, T. Chevolleau, R. Bouyssou, +4

Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena

Materials ScienceChemical EngineeringFluorocarbon EtchingEngineeringCorrosion +13

A new damascene architecture for high-performance metal–insulator–metal capacitors integration

A. Farcy, J. Torrès, V. Arnal, +6

Microelectronic Engineering

Materials ScienceElectrical EngineeringNew Damascene ArchitectureEngineeringElectronic Packaging +2

High performance k=2.5 ULK backend solution using an improved TFHM architecture, extendible to the 45nm technology node

Robert Fox, O. Hinsinger, E. Richard, +28

Low-power ElectronicsImproved Tfhm ArchitectureElectrical EngineeringEngineeringVlsi Design +11

Multidimensional hybrid software-in-the-loop modeling approach for experimental analysis of a floating offshore wind turbine in wave tank experiments

Félicien Bonnefoy, Vincent Leroy, Mohammad Rasool Mojallizadeh, +3

Ocean Engineering