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Characterization and integration of a CVD porous SiOCH (k<2.5) with enhanced mechanical properties for 65 nm CMOS interconnects and below

Materials ScienceElectrical EngineeringEngineeringAdvanced Packaging (Semiconductors)Enhanced Mechanical PropertiesNanoelectronicsSurface ScienceApplied PhysicsPorosityNm Cmos InterconnectsSemiconductor Device FabricationCvd Porous SiochElectronic PackagingSilicon On InsulatorMicroelectronicsInterconnect (Integrated Circuits)