Silicon Device Scaling to the Sub-10-nm Regime

M. Ieong, B. Doris, J. Kedzierski, +2

Science

Device SpeedElectrical EngineeringSilicon Device ScalingEngineeringUltrathin Channel +11

Six-band k⋅p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness

Massimo V. Fischetti, Zhibin Ren, P. M. Solomon, +2

Journal of Applied Physics

Materials ScienceSurface CharacterizationEngineeringSi ThicknessPhysics +13

Ultrathin high-K gate stacks for advanced CMOS devices

E. P. Gusev, D. A. Buchanan, E. Cartier, +20

EngineeringVlsi DesignSilicon On InsulatorSemiconductor DeviceNanoelectronics +14

Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs

K. Rim, K. Chan, L. Shi, +17

Materials EngineeringUltra-thin Strained SiElectrical EngineeringTensile-strained Si LayerEngineering +10

Measurement of the effect of self-heating in strained-silicon MOSFETs

K.A. Jenkins, K. Rim

IEEE Electron Device Letters

Electrical EngineeringEngineeringChannel TemperatureBias Temperature InstabilityApplied Physics +7

Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

K. Rim, J. O. Chu, H. Chen, +16

Electrical EngineeringEngineeringStrained Si DevicesNanoelectronicsBias Temperature Instability +9

Transconductance enhancement in deep submicron strained Si n-MOSFETs

K. Rim, Judy L. Hoyt, J. F. Gibbons

Semiconductor TechnologyElectrical EngineeringTransconductance EnhancementChannel DopingEngineering +8

Low field mobility characteristics of sub-100 nm unstrained and strained Si MOSFETs

K. Rim, M. Longstreet, A. Mocuta, +1

Electrical EngineeringEngineeringNanoelectronicsBias Temperature InstabilityApplied Physics +7

Channel doping impact on FinFETs for 22nm and beyond

C.-H. Lin, R. Kambhampati, Robert J. Miller, +12

Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies

L.T. Su, John Pellerin, Shih-Fen Huang, +42

EngineeringVlsi DesignSilicon On InsulatorInterconnect (Integrated Circuits)Advanced Packaging (Semiconductors) +14