Z. Chbili

Modeling Early Breakdown Failures of Gate Oxide in SiC Power MOSFETs

Z. Chbili, Asahiko Matsuda, Jaafar Chbili et al. · IEEE Transactions on Electron Devices · 2016 · 88 citations

Engineering, Root Cause, Sic Power Mosfets +19

Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio

D. K. Mohata, R. Bijesh, Yunhai Zhu et al. · 2012 · 60 citations

Semiconductor Technology, Gate Stack, Electrical Engineering +14

SOI Field-Effect Diode DRAM Cell: Design and Operation

Ahmad Z. Badwan, Z. Chbili, Yang Yang et al. · IEEE Electron Device Letters · 2013 · 56 citations

Dynamic Ram Cell, Electrical Engineering, Non-volatile Memory +7

Time Dependent Dielectric Breakdown in High Quality SiC MOS Capacitors

Z. Chbili, Kin P. Cheung, J. P. Campbell et al. · Materials science forum · 2016 · 31 citations

Materials Engineering, Sio 2, Electrical Engineering +12

Device reliability metric for end-of-life performance optimization based on circuit level assessment

A. Kerber, P. Srinivasan, S. Cimino et al. · 2017 · 27 citations

Engineering, Computer Architecture, Circuit Level Assessment +16