Device reliability metric for end-of-life performance optimization based on circuit level assessment

Abstract

Performance enhancement is critical for offering competitive CMOS solutions for advanced technology nodes. To fully leverage performance enhancement elements the device reliability impact needs to be comprehended on the CMOS circuits like SRAM and ring-oscillators. We reaffirm that time-zero and BTI induced stochastic variation are most critical for SRAM circuits while for logic circuits such as ring-oscillators the focus is on the mean degradation. In addition we explore the impact of self-heating on the correlation of device to circuit degradation for the FinFET device architecture.