A. Kerber - Concepedia

Author

A. Kerber

GlobalFoundries (United States)ORCID

Also Known As

A Kerber, A. KERBER, A. Kerber, Andreas Kerber, Kerber, Andreas

134

Publications

3.4K

Citations

H-Index

Concepts

All Affiliations

GlobalFoundries (United States)IMEC IBM (United States)Infineon Technologies (Germany)IBM Research - Thomas J. Watson Research Center

About

A. Kerber is an author at GlobalFoundries (United States) specializing in engineering, electrical engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	31	72	3.1K
2	Electrical Engineering	30	70	3K
3	Applied Physics	28	53	2.6K
4	Computer Engineering	17	26	757
5	Education	3	3	156

A. Kerber

Publications

3.3K

Citations

H-Index

Page 1

	Year	Citations
Origin of the threshold voltage instability in SiO<sub>2</sub>/HfO<sub>2</sub> dual layer gate dielectrics A. Kerber, E. Cartier, L. Pantisano, IEEE Electron Device Letters Device ModelingElectrical EngineeringEngineeringPhysicsNanoelectronics	2003	357
Reliability Challenges for CMOS Technology Qualifications With Hafnium Oxide/Titanium Nitride Gate Stacks A. Kerber, E. Cartier IEEE Transactions on Device and Materials Reliability Gate StackGate Stack ReliabilityEngineeringSemiconductor DeviceReliability Engineering	2009	186
Passivation and interface state density of SiO2/HfO2-based/polycrystalline-Si gate stacks R. J. Carter, E. Cartier, A. Kerber, Applied Physics Letters Materials ScienceInterface State PassivationEngineeringOxide ElectronicsSurface Science	2003	118
Accurate model for time-dependent dielectric breakdown of high-k metal gate stacks T. Nigam, A. Kerber, Peter Peumans IEEE International Reliability Physics Symposium proceedings Device ModelingDefect ToleranceElectrical EngineeringReliability EngineeringEngineering	2009	114
On the thermal stability of atomic layer deposited TiN as gate electrode in MOS devices Jörgen Westlinder, T. Schram, L. Pantisano, IEEE Electron Device Letters Aluminium NitrideEngineeringAld TinWork FunctionAtomic Layer	2003	112
Stress-induced leakage current and defect generation in nFETs with HfO<inf>2</inf>/TiN gate stacks during positive-bias temperature stress E. Cartier, A. Kerber Positive-bias Temperature StressSemiconductor TechnologyElectrical EngineeringDefect GenerationEngineering	2009	99
Characterization of the V/sub T/-instability in SiO/sub 2//HfO/sub 2/ gate dielectrics A. Kerber, E. Cartier, L. Pantisano, Gate DielectricsElectrical EngineeringSevere Charge TrappingEngineeringPhysics	2003	91
Reliability screening of high-k dielectrics based on voltage ramp stress A. Kerber, L. Pantisano, A. Veloso, Microelectronics Reliability ReliabilityElectrical EngineeringReliability EngineeringDielectricsEngineering	2007	88
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications Siddarth Krishnan, U. Kwon, N. Moumen, Sige ChannelsLow Power ApplicationsEngineeringVlsi DesignIntegrated Circuits	2011	81
Characterization of Fast Relaxation During BTI Stress in Conventional and Advanced CMOS Devices With $\hbox{HfO}_{2}/\hbox{TiN}$ Gate Stacks A. Kerber, K. Maitra, Amlan Majumdar, IEEE Transactions on Electron Devices Fast RelaxationVlsi DesignEngineeringMeasurementComputer Architecture	2008	79

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