M. Assous

Investigation on TSV impact on 65nm CMOS devices and circuits

H. Chaabouni, Maxime Rousseau, Philip R. LeDuc et al. · 2010 · 54 citations

Low-power Electronics, 3D Ic Architecture, Electrical Engineering +14

Enabling technologies for 3D chip stacking

Patrick Leduc, L. Di Cioccio, Barbara Charlet et al. · 2008 · 47 citations

Engineering, Computer Architecture, Interconnect (Integrated Circuits) +20

Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits

L. Cadix, A. Farcy, C. Bermond et al. · 2009 · 43 citations

Engineering, Stacked Dies, Integrated Circuits +18

Warpage control of silicon interposer for 2.5D package application

Kei Murayama, Mitsuhiro Aizawa, K. Hara et al. · 2013 · 42 citations

Etch mechanisms of low dielectric constant polymers in high density plasmas: Impact of charging effects on profile distortion during the etching process

D. Fuard, O. Joubert, L. Vallier et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 2001 · 35 citations

Engineering, Mechanical Engineering, Plasma Processing +16