S. Fang

High performance 14nm SOI FinFET CMOS technology with 0.0174µm<sup>2</sup> embedded DRAM and 15 levels of Cu metallization

C-H. Lin, B. Greene, J. Cai et al. · 2014 · 128 citations

Scaling deep trench based eDRAM on SOI to 32nm and Beyond

G. Wang, D. Anand, Nauman Zafar Butt et al. · 2009 · 45 citations

Electrical Engineering, Engineering, Vlsi Design +9

Dual workfunction fully silicided metal gates

C. Cabral, J. Kedzierski, B.P. Linder et al. · 2004 · 42 citations

Materials Engineering, Materials Science, Electrical Engineering +14

Advanced gate stacks with fully silicided (FUSI) gates and high-k dielectrics. enhanced performance at reduced gate leakage

E. P. Gusev, C. Cabral, B.P. Linder et al. · 2005 · 28 citations

Materials Engineering, Materials Science, Electrical Engineering +15

Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond

X. Chen, S. Fang, Wenli Gao et al. · 2006 · 25 citations

Engineering, Residual Stress, Mechanics Of Materials +16