Joshua Tseng

Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization

Lars‐Åke Ragnarsson, Z. Li, Joshua Tseng et al. · 2009 · 57 citations

Low-power Electronics, Device Modeling, Electrical Engineering +14

Positive and negative bias temperature instability on sub-nanometer eot high-K MOSFETs

Moonju Cho, M. Aoulaiche, R. Degraeve et al. · 2010 · 32 citations

Interface Degradation, Wide-bandgap Semiconductor, Electrical Engineering +13

8Å T<inf>inv</inf> gate-first dual channel technology achieving low-V<inf>t</inf> high performance CMOS

L. Witters, Shinji Takeoka, S. Yamaguchi et al. · 2010 · 27 citations

Low-power Electronics, Electrical Engineering, Sub Xmlns +14

6Å EOT Si<inf>0.45</inf>Ge<inf>0.55</inf> pMOSFET with optimized reliability (V<inf>DD</inf>=1V): Meeting the NBTI lifetime target at ultra-thin EOT

J. Franco, B. Kaczer, Geert Eneman et al. · 2010 · 24 citations

Engineering, Nbti Lifetime Target, Thin Si Cap +17

High Hole Mobility in 65 nm Strained Ge p-Channel Field Effect Transistors with HfO₂ Gate Dielectric

Jérôme Mitard, Brice De Jaeger, Geert Eneman et al. · Japanese Journal of Applied Physics · 2011 · 23 citations

Materials Engineering, High Hole Mobility, Electrical Engineering +11