S. Yamaguchi

8Å T<inf>inv</inf> gate-first dual channel technology achieving low-V<inf>t</inf> high performance CMOS

L. Witters, Shinji Takeoka, S. Yamaguchi et al. · 2010 · 27 citations

Low-power Electronics, Electrical Engineering, Sub Xmlns +14

Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process

J. Wang, Y. Tateshita, Shuji Yamakawa et al. · 2007 · 27 citations

Materials Engineering, Electrical Engineering, Engineering +10

High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates

Y. Tateshita, J. Wang, K. Nagano et al. · 2006 · 25 citations

Low-power Electronics, Electrical Engineering, Semiconductor Device +11

High-Performance Metal/High-$k$ n- and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on (100) Substrates

Satoru Mayuzumi, Shinya Yamakawa, Y. Tateshita et al. · IEEE Transactions on Electron Devices · 2009 · 23 citations

Materials Science, Electrical Engineering, Engineering +11

Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates

Satoru Mayuzumi, J. Wang, Shuji Yamakawa et al. · 2007 · 18 citations

Materials Science, Semiconductor Technology, Electrical Engineering +14